The present invention relates to semiconductor integrated circuits in general, and, more particularly, to semiconductor integrated circuits applicable to LSI""S, such as general purpose processors, digital signal processors, graphics processors and various control processors.
To achieve high performance design automation, gate array and cell-based IC""s are currently in wide use. In particular, one type of a logic circuit referred to as a pass-transistor logic circuit, is known in this field. It is published that the pass-transistor logic circuit has a higher density, lower power consumption and smaller delay time than the CMOS logic circuits that are commonly used as the logic circuits.
So far, pass-transistor logic circuits have been introduced as a Differential Pass-Transistor Logic in the IEEE Journal of Solid-State Circuits, Vol. sc-22, No. 2, April 1987, pp216-pp222 (hereinafter referred to as a first conventional technology); as a Complementary Pass-Transistor Logic in the IEEE Journal of Solid-State Circuits, Vol. sc-25, No. 2, April 1990, pp388-pp395 (hereinafter referred to as a second conventional technology); and as a 1.5-ns 32-b CMOS ALU in Double Pass-Transistor Logic in the IEEE Journal of Solid State Circuits, Vol. 28, No. 11, November 1993, pp1145-pp1151 (hereinafter referred to as a third conventional technology).
Further, a Low-Power Logic Style: CMOS Versus Pass-Transistor Logic has been introduced in the IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, July 1997, pp1079-pp1090 (hereinafter referred to as a fourth conventional technology). An example layout of a pass-transistor logic circuit is introduced in the Principles of CMOS VLSI Designxe2x80x94A Systems Perspective (by H. E. Weste and Kamran Eshraghian, translated by T. Tomisawa and Y. Matsuyama), published on Aug. 30, 1998, Maruzen Co., Ltd., p. 173 (hereinafter referred to as a fifth conventional technology). A circuit design technique that combines a pass-transistor circuit and the abovementioned standard-cell-based design is introduced in the IEEE 1994 Custom Integrated Circuits Conference, pp603-pp606 (hereinafter referred to as a sixth conventional technology).
Further, a circuit design technique that combines a-pass-transistor circuit and the standard-cell-based design by using a logic representation method called a binary decision diagram is introduced in the Institute of Electronics, Information and Communication Engineering, Proceedings of the 1994 IEICE Fall Conference (hereinafter referred to as a seventh conventional technology). A logic circuit cell using a pass-transistor circuit is shown in JP-A-7-130856 (laid-open on May 19, 1995, and corresponding to U.S. Pat. No. 5,581,202) (hereinafter referred to as an eighth conventional technology). A transmission gate multiplexer is disclosed in U.S. Pat. No. 5,162,666 (hereinafter referred to as a ninth conventional technology). A xe2x80x9cPass Transistor Network in MOS Technologyxe2x80x9d is introduced in IEEE 1983 International Symposium on Circuit and Systems, pp509-pp512 (hereinafter referred to as a tenth conventional technology).
FIGS. 4a and 4b show, as an example to be compared, the layout of a cell of a CMOS logic circuit developed by the inventors of this invention. To the knowledge of the present inventors, this layout is not known to the public. In this layout, gate terminals of PMOS and NMOS are arranged in line with each other to reduce the layout area. The inventors conducted a preliminary study on the cell layout based on the above design philosophy to realize an integrated circuit with a small layout area by using pass-transistor circuits.
FIGS. 5a and 5b show the result of a study by the present inventors. In these figures, the source (drain) diffusion layers at the same voltage cannot be used commonly to arrange the gate terminals closer together. Hence, the diffusion layers that cannot be used commonly need to be connected by upper-layer metal wires, giving rise to a problem of increased layout area and wire length. The longer total wire length as well as the increased layout area, in turn, increase the delay time. The object of the present invention is to provide a pass-transistor logic circuit that has a small layout area.
The conventional pass-transistor logic circuit has a problem that because the source (drain) terminal acts as an input terminal, the input signal waveform degrades. Further, because the input capacitance changes depending on the operating conditions, the delay calculation is difficult. To solve these problems, an inverter has been known to be provided to an input terminal of source (drain) terminal (as in the ninth and tenth conventional technology). However, the preliminary study by the inventors has found that this method increases the delay time by as much as the inverters added. Another object of the invention is to provide a pass-transistor logic circuit which is fast and allows easy delay calculation.
The present invention proposes a selector portion layout method to be used during the process of laying out the pass-transistor logic circuit cells of the above construction.
According to one aspect of the present invention, a cell is used that has at least one selector. To fabricate cells with small areas by using only polysilicon wires, or wires of the same material as gate terminals, and first-layer metal wires, the semiconductor circuit of the present invention is laid out according to the following design philosophy.
That is, in the pass-transistor circuit, pMOS""s and nMOS""s that are applied the same signals receive complementary gate signals. The MOS""s with the same drain outputs are arranged to share their diffusion layers.
Further, according to another aspect of the present invention, when there is a plurality of selectors, output buffers are arranged at the ends of the cell, and the selectors are arranged in a direction in which the first power supply line and the second power supply line extend. With this arrangement, if there is a plurality of selectors, the number of the selectors can be increased flexibly in the direction of expansion, thus assuring a systematic layout. This in turn reduces the time required to design the layout of the selectors.
According to a further aspect of the present invention, a signal buffer is connected to the input side of the selector. As a result, all signals entering the pass-transistor circuit become gate signals, which in turn reduce the input capacitance, thus solving the problem of degraded input waveform. This arrangement can also prevent the input capacitance from varying depending on the operation conditions, making it easy to estimate the input capacitance and the delay calculation. This can be expected to shorten the design time.
Further, in this circuit which has the signal buffers connected to the source and drain terminals, because the signal path passing through the gate terminal of the pass-transistor circuit does not pass through the signal buffer, the high speed operation is possible.
According to a further aspect of the present invention, the integrated circuit including the circuit of this invention has power supply lines, of which power supply lines 1, 3, 5, . . . , 2n+1, . . . (n is a natural number) are at the same voltage, and power supply lines 2, 4, 6, . . . , 2n, . . . (n is a natural number) are at the same voltage. Thus, this integrated circuit can coexist with other circuits represented by CMOS circuits.
According to a further aspect of the present invention, the integrated circuit including the circuit of this invention has a latch. Because a signal passing through the gate terminal of the selector does not pass through the signal buffer, a high speed signal transmission between the latches is possible. The circuit of the invention therefore is an important factor in determining the specification of the integrated circuit.
According to a further aspect of the present invention, a signal that has passed through the input buffer now passes through the selector, from which it is transmitted to a plurality of input terminals. This enables the whole integrated circuit to be formed compactly.
According to one embodiment of the circuit of 15 the present invention, the integrated circuit includes a selector 1 and logic gates 1, 2 and also power supply lines 1, 2, 3, 4, 5 and 6 arranged in parallel. Of these power supply lines 1, 3, 5 are virtually at the same voltage and power supply lines 2, 4, 6 are virtually at the same voltage. The selector 1 has PMOS1, 2, and NMOS1, 2, 3, 4; a gate of PMOS1 is controlled by an input signal 1; and a source-drain path of PMOS1 is connected between an operation voltage point 1 and a node 1. A gate of PMOS2 is controlled by an input signal 2; and a source-drain path of PMOS2 is connected between the operation voltage point 1 and a node 2. A gate of NMO@L is controlled by the input signal 1, and a source drain path of NMOS1 is connected between an operation voltage point 2 and the node 1. A gate of NMOS2 is controlled by the input signal 2, and a source-drain path of NMOS2 is connected between the operation voltage point 2 and the node 2. A gate of NMOS3 is controlled by an input signal 3, and a source-drain path of NMOS3 is connected between the node 1 and a node 3. A gate of NMOS4 is controlled by an input signal 4, and a source-drain path of NMOS4 is connected between the node 2 and the node 3. The node 3 is connected to input terminals of the logic gate 1 and the logic gate 2.
Further, if the circuit is formed as a sequential circuit, it is characterized as follows. It has first and second temporary memory circuit; a first power supply line is formed in a horizontal direction; and a second power 15 supply line is formed parallel to the first power supply line. The second temporary memory circuit is controlled by the same clock signal as is used for the first temporary memory circuit. A data output node 01 of the first temporary memory circuit controls the gate terminals of NMOS1 and PMOS2. The source-drain path of NMOS1 is connected between nodes n1 and n2; the source-drain path of PMOS2 is connected between nodes n2 and n3; the source-drain path of PMOS3 is connected between the first power supply line and the node n1; the source-drain path of NMOS3 is connected between the second power supply line and the node n1; a signal of node n4 controls the gate terminals of PMOS3 and NMOS3; the source-drain path of PMOS4 is connected between the first power supply line and the node n3; the source-drain path of NMOS4 is connected between the second power supply line and the node n3; a signal of node n5 controls the gate terminals of PMOS4 and NMOS 4; the source-drain path of NMOS2 is connected to the nodes n2 and n3; the source-drain path of PMOS1 is connected between the nodes n1 and n2; a signal of node n6 controls the gate terminals of PMOS1 and NMOS2; a signal of node n2 controls the gate terminals of PMOS5 and NMOS5 and is applied to input the terminals of other logic gates; a source-drain path of PMOS5 is connected between the first power supply line and node n7; a source-drain path of NMOS5 is connected between the second power supply line and the node n7; a source-drain path of NMOS8 is connected between nodes n7 and n9; a source-drain path of NMOS8 is connected between node n7 and n9; a source-drain path of PMOS9 is connected between nodes n9 and n11; a source-drain path of NMOS9 is connected between nodes n9 and n11; a signal of node n8 controls the gate terminals of PMOS9 and NMOS8; a signal of node n10 controls the gate terminals of PMOS8 and NMOS9; a signal of node n12 controls the gate terminals of PMOS8 and NMOS8; a source-drain path of PMOS8 is connected between the first power supply line and node n11; a source-drain path of NMOS 8 is connected between the second power supply line and node n11; a signal of node n15 controls the gate terminals of PMOS9 and NMOS9; a source-drain path of PMOS9 is connected between the first power supply line and node n14; a source-drain path of NMOS9 is connected between the second power supply line and node n14; a source-drain path of PMOS10 is connected between nodes n14 and n17; a source-drain path of NMOS10 is connected between nodes n14 and n17; a source-drain path of PMOS11 is connected between nodes n9 and n17; a source-drain path of NMOS11 is connected between nodes n9 and n17; a signal of node n13 controls the gate terminals of PMOS10 and NMOS11; a signal of node n16 controls the gate terminals of PMOS11 and NMOS10; a signal of node n18 controls the gate terminals of PMOS15 and NMOS15; a source-drain path of PMOS15 is connected between the first power supply line and node n18; a source-drain path of NMOS15 is connected between the second power supply line and node n18; a source-drain path of PMOS13 is connected between nodes n20 and n22; a source-drain path of NMOS13 is connected between nodes n20 and n22; a source-drain path of PMOS14 is connected between nodes n18 and n20; a source-drain path of NMOS14 is connected between nodes n18 and n20; a signal of node n17 controls the gate terminals of PMOS13 and NMOS14; a signal of node n21 controls the gate terminals of PMOS14 and NMOS13; a signal of node n23 controls the gate terminals of PMOS12 and NMOS12; a source-drain path of PMOS12 is connected between the first power supply line and node n22; a source-drain path of NMOS12 is connected between the second power supply line and node n22; and a signal of node n20 is connected between the inputs of the second temporary memory circuit.
FIGS. 7a-7c are circuit diagrams of logic circuits to which the present invention is applicable. FIG. 7a shows a circuit in which a signal is amplified after it has passed through the selector. FIG. 7c shows a circuit in which a signal is amplified before it passes through the selector. As a result, in the circuit of FIG. 7c, the input capacitance produced when the circuit receives drain inputs is only that of the gates of the input buffers, thus significantly reducing the input capacitance. FIG. 7b shows a circuit with a plurality of selectors. The layouts suited for these circuits will be described in detail.